The present invention relates to a clock signal supply system, or more in particular to a clock signal supply system suitably used with a clock supply section of a main-frame computer capable of high-speed arithmetic processing.
In a conventional method generally employed for adjusting the phase of a clock signal for a mainframe computer facing the problem of a phase shift, the waveform of the clock signal for each destination is observed manually with an oscilloscope or the like to set the phase to a predetermined value.
A method not using any oscilloscope has been disclosed, on the other hand, in JP-A-61-39619, an application for which was filed by Nippon Electric Co., Ltd. on Jul. 30, 1984, in which a clock supply circuit constitutes a ring oscillator, from the oscillation frequency of which a signal delay time of the clock supply circuit is detected to adjust the signal delay to a predetermined value.
Manual phase adjustment of a clock signal with an oscilloscope or the like requires a considerable labor and therefore is difficult to effect at a great number of points. It is thus inevitable to conduct phase adjustment at several tens to several hundreds of centralized relay points with the signal sent unadjusted to destinations at further ends. The resultant variations in signal transmission time without adjustment constitutes a limit of the clock skew reduction.
If the adjustment procedure which has thus far been handled manually is to be automated directly, it is necessary to place a probe in contact with a waveform observation point corresponding to each adjustment point sequentially, thereby requiring a mechanical positioning means for contact. In the case where a great number of adjustment points is involved, therefore, contact points would be so congested that the probe positioning procedure requires a high accuracy and rapidity, thus making the realization thereof difficult. If a signal line for the probe is installed separately for each waveform observation point, a mechanical positioning procedure would be eliminated. Such a method, however, would require that the signal transmission time for the signal lines for the probes connected to the waveform observation points all be uniform. The process of making uniform the signal transmission time for the signal lines connected to the waveform observation points requires substantially the same amount of labor as the phase asjustment of clock signals.
The method disclosed in JP-A-61-39619 described above, which also requires that all signal transmission time of the cables for returning from destinations to input points be uniform, poses the same problem as the aforementioned one after all.
Especially in a main-frame computer, the machine cycle is expected to shorten more and more with the increase in the speed of arithmetic processing. As a result, it is necessary to increase the phase adjustment points for reducing the clock skew. In view of this, the above-mentioned problem provides an important task to be overcome.
The conventional systems thus have the shortcoming that an increase in the number of phases of a clock signal leads to a proportionately increased number of adjustment points, thereby requiring an increased expenditure of labor for adjustment. On the other hand, a higher speed of a clock signal causes the rise time or fall time to approach the clock period with the result that a fall may begin before a sufficient voltage rise at the destinations of the clock signals. The clock signal amplitude is thus reduced with less noise margin, sometimes extinguishing the clock signal itself. Phase adjustment therefore becomes more difficult. This phenomenon is liable to occur especially in a long signal line between a clock source and each destination where the load or skin effect is conspicuous. In this respect, the method of adjusting the phase of a clock signal disclosed in JP-A-61-39650 and JP-A-61-39651, applications filed by Fujitsu, Ltd. in Japan on Jul. 28, 1984 and an example of a variable delay circuit disclosed in JP-A-62-24410, an application which was filed by Mitsubishi Electric Corporation on Apr. 14, 1986, do not provide sufficient means to prevent the variations in pulse duration or attenuation of the signal amplitude or extinction of the signal.
Automatic adjustment of the phase of a clock signal for a computer or the like often gives rise to a hazard or other difficulties if the control mechanism for the automatic adjustment is kept in operation. After complete adjustment, therefore, it is desirable to stop the control mechanism. In that case, however, it is difficult to compensate for a small phase shift that occurs after shut down of the control mechanism. The resulting variation, though small as compared with the phase shift to be adjusted, makes up a proportion not ignorable if the tolerance against the phase shift is reduced. In order to compensate for this, it is necessary to decide whether the phase shift is of a degree below the tolerance and, if it exceeds the tolerance, to issue an alarm signal for readjustment.
Conventional phase comparator circuits, as disclosed in Analog Data Manual (June 1983) of Signetics, for example, have only the function to decide which of two given signals is advanced but do not any function to detect the phase difference between them or to issue an alarm signal when the difference is considerable.